TSMC Prepares Five 3nm Process Technologies, Adds FinFlex for Design Flexibility

Taiwan Semiconductor Manufacturing Co. kicked off Thursday with its TSMC Technology Symposium in 2022, where the company traditionally shares its process technology roadmaps, as well as its future expansion plans. One of the key things TSMC is announcing today is its leading nodes belonging to the N3 (3nm class) and N2 (2nm class) families that will be used in the coming years to create advanced CPUs, GPUs and SoCs.

N3: five nodes in the next three years

As manufacturing processes become more complex, so do their pathfinding, research and development times, so we no longer see a brand new hub appearing every two years at TSMC and other foundries. With N3, TSMC’s new node launch cadence will extend to approximately 2.5 years, while with N2 it will extend to approximately three years.

This means that TSMC must offer improved versions of N3 to meet the needs of its customers who are still looking for an improvement in performance per watt and an increase in transistor density every year or so. Another reason why TSMC and its customers require multiple versions of N3 is because the foundry’s N2 relies on all-new gate-all-round field effect transistors (GAA FETs) implemented using nanosheets, which is expected to increase costs with will entail, new design methodologies, new IP and many other changes. While developers of cutting-edge chips will quickly jump to N2, many of TSMC’s more rank & file customers will be sticking with various N3 technologies for years to come.

At the TSMC Technology Symposium 2022, the foundry talked about four N3-derived fabrication processes (for a total of five 3nm class nodes) – N3E, N3P, N3S and N3X – that will be introduced in the coming years. These N3 variants are planned to deliver improved process windows, higher performance, higher transistor densities and increased voltages for ultra-high performance applications. All of these technologies support FinFlex, a TSMC “secret sauce” feature that greatly improves their design flexibility and enables chip designers to accurately optimize performance, power consumption, and cost.

Advertised PPA Enhancements of New Process Technologies
Data announced during conference calls, events, press conferences and press releases TSMC N4
N5 N4P
N5 N4P
N4 N4X
N5 N4X
N4P N3
N5 N3E
N5 Power lower -22% – ? ? -25-30% -34% Performance up +11% +6% +15%
more +4%
or more +10-15% +18% Logical area

Reduction* %

Logical density*















Production 2022 2023 H2 2022 2023 2023 H2 2022 Q2/Q3 2023

*Note that TSMC didn’t start publishing separate transistor density improvements for analog, logic, and SRAM until around 2020. Some numbers still represent a ‘mixed’ density consisting of 50% logic, 30% SRAM and 20% analog.

N3 and N3E: on track for HVM

TSMC’s first 3nm class node is called N3 and it is on track to begin high-volume manufacturing (HVM) in the second half of this year. The actual chips are expected to be delivered to customers in early 2023. This technology is primarily aimed at early adopters (read: Apple and the like) who can invest in leading edge designs and would take advantage of the performance, power, area (PPA) benefits offered by leading nodes. But because it is tailored for certain types of applications, N3 has a relatively narrow process window (a set of parameters that yield a defined result), which may not be suitable for all applications in terms of yields.

This is when N3E comes into play. The new technology improves performance, lowers power and expands the process window, resulting in higher yields. But the trade-off is that the node has a slightly lower logic density. Compared to N5, N3E offers a 34% reduction in power consumption (at the same speed and complexity) or an 18% performance improvement (at the same power and complexity), and will increase the logic transistor density by 1.6x.

It is noteworthy that, based on data from TSMC, N3E will offer higher clock speeds than even N4X (expected in 2023). However, the latter also supports ultra-high drive currents and voltages above 1.2 V, after which it can offer unbeatable performance, but with very high power consumption.

Overall, N3E appears to be a more versatile node than N3, so it’s not surprising that TSMC currently has more ‘3nm tape outs’ than it had with its 5nm class node at a similar point in its development.

Risk production of chips with N3E will begin in the coming weeks (ie in Q2 or Q3 2022) with HVM set for mid-2023 (again, TSMC does not disclose whether we are talking about Q2 or Q3). So expect commercial N3E chips to be available in late 2023 or early 2024.

N3P, N3S and N3X: Performance, Density, Tension

N3’s improvements don’t stop at N3E. TSMC plans to release N3P, a performance-enhanced version of the manufacturing process, around 2024, as well as N3S, the density-boosting flavor of this node. Unfortunately, TSMC is currently not disclosing what improvements these variants will offer compared to baseline N3. At its Technology Symposium 2022, TSMC didn’t even show N3S in its roadmap and was only mentioned by Kevin Zhang in a conversation. With all this in mind, trying to guess the features of N3S really isn’t a good thing.

Finally, for those customers who need ultra-high performance regardless of power consumption and cost, TSMC will offer N3X, which is essentially an ideological successor to N4X. Again, TSMC does not disclose any details about this node other than that it will support high drive currents and voltages. We could speculate that N4X could use backside power delivery, but since we are talking about a FinFET based node and TSMC is only going to implement backside power rail in nanosheet based N2, we are not sure if this is the case. Nevertheless, TSMC probably has some advantages up its sleeve when it comes to voltage boosts and performance improvements.

FinFlex: the secret sauce of N3

Speaking of improvements, we should definitely mention TSMC’s secret sauce for N3: FinFlex technology. In short, FinFlex allows chip designers to fine-tune their building blocks for higher performance, higher density and lower power.

Update 6/17: The first version of the story incorrectly referred to standard cells and blocks as transistors, which has been corrected.

When using a FinFET-based node, chip designers can choose between several libraries with different standard cells. A standard cell is the most basic building block that performs a Boolean logic or storage function and consists of a group of transistors and interconnects. From a mathematical point of view, the same function can be performed (with the same result) using a standard cell with different configurations. But from the point of view of manufacturability and operation, different standard cell configurations are characterized by different performance, power consumption and area. When developers need to minimize mold size and save energy at the expense of performance, they use small standard cells. But when they need to maximize performance as opposed to die size and higher power, they use large standard cells.

Currently, chip designers must adhere to one library/standard cells for the entire chip or block in a SoC design. For example, CPU cores can be implemented using 3-2 fin blocks to make them run faster, or 2-1 fin standard cells to reduce their power consumption and footprint. This is a fair trade-off, but it’s not ideal for all cases, especially if we’re talking about 3nm class nodes that will be more expensive to run than existing technologies.

For N3, TSMC’s FinFlex technology enables chip designers to mix and match different types of standard cells within one block to fine-tune performance, power consumption and area. For complex structures such as CPU cores, such optimizations offer many opportunities to improve core performance while still optimizing die sizes. So we’re curious to see how SoC designers can take advantage of FinFlex in the looming N3 era.

FinFlex is not a substitute for node specialization (performance, density, voltages) as process technologies have greater differences than the ibraries or transistor structures within a single process technology, but FinFlex appears to be a good way to improve the performance, power and cost for the N3. node of TSMC. Ultimately, this technology will bring the flexibility of FinFET-based nodes slightly closer to nanosheet/GAAFET-based nodes, which are expected to offer tunable channel widths to get higher performance or reduce power consumption.


Like TSMC’s N7 and N5, N3 will be another family of durable nodes for the world’s largest semiconductor contrast maker. Especially with the jump to nanosheet-based GAAFETs coming in at 2nm for TSMC, the 3nm family will be the company’s last family of “classic” leading FinFET nodes, and one that many customers will stick with for several years ( or more). That, in turn, is why TSMC is preparing multiple versions of N3 tailored for different applications – as well as FinFlex technology to give chip designers some extra flexibility in their designs.

The first N3 chips will go into production in the coming months and hit the market in early 2023. Meanwhile, TSMC will continue to manufacture semiconductors using its N3 nodes long after it introduces its N2 process technology in 2025.

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