N2 to start with only GAAFETs, later add Power Delivery to the back

When TSMC introduced its N2 (2 nm class) process technology earlier this month, the company outlined how the new node would be built on the back of two new advanced fab techniques: gate all-round transistors and backside power rails. But, as we’ve since learned from last week’s EU symposium, TSMC’s plans are a bit more nuanced than first announced. Unlike some of their rivals, TSMC will not implement both technologies in the first version of their N2 node. Instead, the first iteration of N2 will implement only gate-all-round transistors, with power delivery at the back with a later version of the node.

So far, TSMC has mentioned two distinguishing features of N2: nano sheet gate-all-around (GAA) transistors and backside power rails. GAA transistors have two unique advantages over FinFETs: they solve many challenges related to the leakage current as the channels of GAAFET are horizontal and surrounded by gates on all four sides. Meanwhile, the rear power rail provided improved power to transistors, increasing performance and reducing power consumption.

But it turns out that TSMC has no plans to start with both nanosheet GAA transistors and backside power rails in the first generation of its N2 process technology. As the company revealed at their EU symposium last week, the first-generation N2 will only feature gate-all-round transistors. On the other hand, the rear power delivery will come later with more advanced implementations of N2.

At this point, the company hasn’t said too much about why they aren’t rolling out backside power delivery as part of their first N2 node. But in discussing the split, TSMC has noted that back-end power delivery will eventually add additional process steps, which the company is seemingly trying to avoid on their first attempt with GAAFETs.

The lack of rear power delivery in the original version of the N2 fabrication technology may explain N2’s rather mediocre performance improvement compared to the N3E node. While for high-performance computing (CPUs, accelerators, etc.) a 10% to 15% performance increase at the same power and complexity may not seem impressive, a 25% to 30% power loss at the same speed and complexity seems to be very good for mobile applications.

Advertised PPA Enhancements of New Process Technologies
Data announced during conference calls, events, press conferences and press releases TSMC N5
N7 N3
N5 N3E
N5 N2
N3E Power -30% -25-30% -34% -25-30% Performance +15% +10-15% +18% +10-15% Chip Density* ? ? ~1.3X >1.1X Volume
Production Q2 2022 H2 2022 Q2/Q3 2023 H2 2025

*Chip density published by TSMC reflects ‘mixed’ chip density consisting of 50% logic, 30% SRAM and 20% analog.

Since TSMC always offers multiple versions of its nodes, it is not surprising that TSMC has several variants planned for N2. Nevertheless, it’s a little odd to see TSMC going quite a long way toward backwards power delivery.

Compared to and unlike the competition, this will be a notable difference from how rival Intel plans to handle their own GAAFET/backside power transition with the Intel 20A process. Intel plans to roll out its GAA RibbonFET transistors and PowerVia interconnects together in mid-2024 — even going so far as to create an internal pseudo-node to focus on RibbonFET development. TSMC, on the other hand, takes a more cautious approach to risks and innovations, which may cause TSMC to move at a slower pace, but it is also an approach that has traditionally been a better fit for TSMC’s need to deliver more constant and consistent updates of its fantastic offer.

And while we’re still a few years away, it will be interesting to see what this means for the competitiveness of TSMC’s first-generation N2 node. Will a GAAFET process with no backend power present a significant disadvantage? We are currently planning to find the answer in the second half of 2025, when TSMC’s first N2 node is expected to go into high volume (HVM) production.

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